The present invention relates to a dynamic circuit for high-speed operation and, more particularly, to a dynamic flip-flop circuit and a dynamic latch circuit operable at a high speed while consuming a minimum of power.
A dynamic circuit of the kind described is used in the high-speed circuits art using a CMOS (complementary Metal Oxide Semiconductor) process. Various kinds of dynamic latch circuits and dynamic flop-flop circuits operable at high speeds are taught in "High-Speed CMOS Circuit Technique", IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, February, 1989, pp. 62-70. However, the circuits taught in this document each has a problem that the rise time and fall time of its output signal are not balanced and cause the duty cycle to deviate from 50%, degrading the balance of circuit operation.